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EM680FU16A Series
Low Power, 512Kx16 SRAM
Document Title
512K x16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
0.0 0.1
History
Initial Draft 0.1 Revision
Draft Date
Sep. 28 , 2007
Remark
Preliminary
Fix typo error
Nov. 12, 2007
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1
EM680FU16A Series
Low Power, 512Kx16 SRAM FEATURES
* * * * * * Process Technology : 0.15m Full CMOS Organization : 512K x 16 bit Power Supply Voltage : 2.7V ~ 3.3V Low Data Retention Voltage : 1.5V(Min.) Three state output and TTL Compatible Package Type : 48-FPBGA 8.0x10.0
GENERAL DESCRIPTION
The EM680FU16A families are fabricated by EMLSI's advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family EM680FU16A-45LF EM680FU16A-55LF EM680FU16A-70LF Operating Temperature Industrial (-40 ~ 85oC) Industrial (-40 ~ 85oC) Industrial (-40 ~ 85oC) Vcc Range 2.7V~3.3V 2.7V~3.3V 2.7V~3.3V Speed Standby (ISB1, Typ.) 2 A 2 A 2 A Operating (ICC1.Max) 3mA 3mA 3mA PKG Type 48-FPBGA 48-FPBGA 48-FPBGA
45ns 55ns 70ns
PIN DESCRIPTION
1 A B C D E F G H 2 3 4 5 6
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
LB I/O9
OE UB
A0 A3 A5 A17 DNU A14 A12 A9
A1 A4 A6 A7 A16 A15 A13 A10
A2 CS1 I/O2 I/O4 I/O5 I/O6 WE A11
CS2
Row Select
I/O1 I/O3 VCC VSS I/O7 I/O8
I/O10 I/O11 VSS VCC I/O12 I/O13
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
VCC VSS
Memory Array 2048 x 4096
I/O1 ~ I/O8 I/O9 ~ I/O16
Data Cont
Data Cont
I/O Circuit Column Select
I/O15 I/O14 I/O16 DNU A18 A8
A11 A12 A13 A14 A15 A16 A17 A18
DNU
WE OE UB LB CS1 CS2
48-FPBGA : Top view (ball down)
Control Logic
Name
Function
Name Vcc Vss UB LB
Function Power Supply Ground Upper Byte (I/O9~16) Lower Byte (I/O1~8)
CS1,CS2 Chip select inputs OE WE A0~A18 Output Enable input Write Enable input Address Inputs
I/O1~I/O16 Data Inputs/outputs
DNU Do Not Use
2
EM680FU16A Series
Low Power, 512Kx16 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter
Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature
Symbol
VIN, VOUT VCC PD TA
Minimum
-0.2 to 4.0V -0.2 to 4.0V 1.0 -40 to 85
Unit
V V W
o
C
* Stresses greater than those listed above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS1 H X X L L L L L L L L CS2 X L X H H H H H H H H OE X X X H H L L L X X X WE X X X H H H H H L L L LB X X H L X L H L L H L UB X X H X L H L L H L L I/O1-8 High-Z High-Z High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Stand by Stand by Active Active Active Active Active Active Active Active
NOTE: X means don't care. (Must be low or high state)
3
EM680FU16A Series
Low Power, 512Kx16 SRAM RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter Supply voltage Ground Input high voltage Input low voltage
1. 2. 3. 4.
Symbol VCC VSS VIH VIL
Min 2.7 0 2.2 -0.23)
Typ 3.0 0 -
Max 3.3 0 VCC + 0.22) 0.6
Unit V V V V
TA= -40 to 85oC, otherwise specified. Overshoot: VCC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item Input capacitance Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO ICC ICC1 Average operating current ICC2
VIN=VSS to VCC CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH VIO=VSS to VCC IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL Cycle time=1s, 100% duty, IIO=0mA, CS1<0.2V, LB<0.2V or/and UB<0.2V, CS2>VCC-0.2V, VIN<0.2V or VIN>VCC-0.2V Cycle time = Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL , VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA CS1=VIH, CS2=VIL, Other inputs=VIH or VIL CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled) or 0VTest Conditions
Min -1 -1 45ns 55ns 70ns 2.2 -
Typ -
Max 1 1 3 3 40 30 20 0.4 0.3
Unit uA uA mA mA
mA
Output low voltage Output high voltage Standby Current (TTL)
VOL VOH ISB
V V mA
Standby Current (CMOS)
ISB1
LF
-
2
15
uA
4
EM680FU16A Series
Low Power, 512Kx16 SRAM
VTM3) R12)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL = 100pF+ 1 TTL (70ns) CL1) = 30pF + 1 TTL (45ns/55ns) 1. Including scope and Jig capacitance R2=3150 ohm 2. R1=3070 ohm, 3. VTM=2.8V 4. CL = 5pF + 1 TTL (measurement with tLZ1,2, tHZ12, tOLZ, tOHZ, tWHZ)
CL1)
R22)
READ CYCLE (Vcc =2.7 to 3.3V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Read cycle time Address access time Chip select to output Output enable to valid output UB, LB Access time Chip select to low-Z output UB, LB enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB, LB disable to high-Z output Output disable to high-Z output Output hold from address change
Symbol
tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH
45ns Min 45 5 5 5 0 0 0 10 Max 45 45 30 45 20 20 20 Min 55 5 5 5 0 0 0 10
55ns Max 55 55 35 55 20 20 20 Min 70 5 5 5 0 0 0 10
70ns Max 70 70 35 70 25 25 25 -
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
WRITE CYCLE (Vcc =2.7 to 3.3V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Write cycle time Chip select to end of write Address setup time Address valid to end of write UB, LB valid to end of write Write pulse width Write recovery time Write to ouput high-Z Data to write time overlap Data hold from write time End write to output low-Z
Symbol
tWC tCW1, tCW2 tAS tAW tBW tWP tWR tWHZ tDW tDH tOW
45ns Min 45 45 0 45 45 45 0 0 25 0 5 Max 20 Min 55 45 0 45 45 45 0 0 30 0 5
55ns Max 20 Min 70 60 0 60 60 55 0 0 30 0 5
70ns Max 25 -
Unit
ns ns ns ns ns ns ns ns ns ns ns
5
EM680FU16A Series
Low Power, 512Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL,
tRC Address tAA tOH Data Out
Previous Data Valid Data Valid
CS2=WE=VIL)
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC Address tAA CS1 CS2 tBA UB,LB tOE OE tOLZ
Data Valid
tOH tCO1,2
tHZ1,2
tBHZ
tOHZ
Data Out
High-Z
tBLZ tLZ1,2
NOTES (READ CYCLE) 1. tHZ1,2 and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to device interconnection.
6
EM680FU16A Series
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC Address tCW1,2(2) CS1 CS2 tAW tBW UB,LB tWP(1) WE tAS(3) Data in High-Z tWHZ Data out Data Undefined tDW
Data Valid
tWR(4)
tDH High-Z tOW
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
tWC Address tAS(3) CS1 CS2 tAW tBW UB,LB tWP(1) WE tDW Data in
Data Valid
tCW1,2(2)
tWR(4)
tDH
Data out
High-Z
High-Z
7
EM680FU16A Series
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
tWC Address tCW1,2(2) CS1 tWR(4)
CS2 tAW tBW UB,LB tAS(3) WE tDW Data in Data out High-Z
Data Valid
tWP(1)
tDH
High-Z
NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition among CS1 goes high, CS2 goes low and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW1 is measured from the CS1 going low or CS2 going high to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high or CS2 going low.
8
EM680FU16A Series
Low Power, 512Kx16 SRAM DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Symbol
VDR IDR tSDR tRDR
Test Condition
CS1 Vcc-0.2V 1) VCC=1.5V, CS1 Vcc-0.2V 1) See data retention wave form
Min
1.5 0 tRC
Typ
-
Max
3.3 4 -
Unit
V uA ns
1. CS1 Vcc-0.2V , CS2 Vcc-0.2V (CS1 controlled) or CS2 < 0.2V (CS2 controlled)
DATA RETENTION WAVE FORM
tSDR Vcc 2.7V tRDR
Data Retention Mode
2.2V VDR CS1, LB / UB GND
CS1 > Vcc-0.2V
Vcc 2.7V CS2 VDR 0.4V GND tSDR
Data Retention Mode
tRDR
CS2 < 0.2V
9
EM680FU16A Series
Low Power, 512Kx16 SRAM
Unit: millimeters
PACKAGE DIMENSION
48 Ball Fine Pitch BGA (0.75mm ball pitch) Top View
B 6 A #A1 B C C C1 C B/2 D E C1/2 F G H 5 4
Bottom View
B B1 3 2 1 0.5
A1 index Mark
Side View
0.26 E2 D
0.25 Typ.
Detail A
A Y
E E1
Min A B B1 C C1 D E E1 E2 Y 7.90 9.90 0.30 1.00 -
Typ 0.75 8.00 3.75 10.00 5.25 0.35 1.04 0.79 0.25 -
Max 8.10 10.10 0.40 1.10 0.08
NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75x0.75) (typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max)
10
0.79Typ.
C
0.5
EM680FU16A Series
Low Power, 512Kx16 SRAM
SRAM PART CODING SYSTEM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory 2. Product Type 3. Density 4. Function 5. Technology 6. Operating Voltage
1. Memory Component EM --------------------- Memory 2. Product Type 6 ------------------------ SRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 3 ------------- Single CS / LBB, UBB(tBA=tOE) 4 ------------- Single CS / LBB, UBB(tBA=tCO) 5 ------------- Dual CS / LBB, UBB(tBA=tOE) 6 ------------- Dual CS / LBB, UBB(tBA=tCO) 5. Technology F ------------------------- Full CMOS 6. Operating Voltage T ------------------------- 5.0V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V
11. Power 10. Speed
9. Package 8. Generation 7. Organization
7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 8. Generation Blank ----------------A ----------------------B ----------------------C ----------------------D ----------------------E ----------------------F ----------------------G ---------------------1st generation 2nd generation 3rd generation 4th generation 5th generation 6th generation 7th generation 8th generation
9. Package Blank ---------------- KGD, 48&36FpBGA S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 V ---------------------- 32 SOP 10. Speed 45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ---------------------45ns 55ns 70ns 85ns 100ns 120ns
11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free & Green) L ---------------------- Low Power S ---------------------- Standard Power
11

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